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IC Packaging
Overview:
Historically, silicon design and package design were treated as separate activities. Design teams often transferred a minimal subset of design data between platforms, a process that was manual, inefficient, and time-consuming. To minimize redesigns or iterations of the package substrate, package planning must begin early in the chip design phase, with active collaboration from package engineers. This includes estimating or defining factors such as die/package size, pin count, die thickness, I/O placement, power requirements, and signal integrity considerations.
Package specifications generally fall into three categories: mechanical, electrical, and thermal. These factors are interrelated and must be integrated into the design process rather than addressed in isolation. IC package development or substrate design process is outlined using a flowchart, which details the sequence of steps, along with the required input and output files at each stage. Typically, the package netlist includes a comprehensive list of bumps or bond pads with their x/y-coordinates, net names, balls, signals, impedance values, DC current requirements, and skew limits for balanced (matched) nets.
Electrical Properties
The electrical aspects of package design primarily address factors influencing chip performance and signal integrity. Below are key considerations in the package development process:
1. Package Type (e.g., flip chip, wire bond)
Different package types exhibit varying electrical performance due to package parasitics such as self-inductance, impedance, and capacitance of data traces, as well as power/ground plane inductance. Flip chips with substrates featuring multiple power/ground planes typically provide superior performance compared to wire bond packages, owing to their lower parasitics. Ball Grid Arrays (BGAs) generally offer lower parasitics than Pin Grid Arrays (PGAs).
2. Number of Layers
The number of signal layers depends on design complexity, routability constraints, and chip orientation. While additional layers may increase cost, it is critical to ensure sufficient ground and power planes when routing data and control traces across three or more layers.
3. Number of Power/Ground Planes
A ground plane close to data paths is recommended to shorten signal return paths, reducing parasitics and achieving consistent impedance matching. This is typically defined during the substrate stack-up design.
4. Impedance Matching Per Layer
Impedance requirements for each data track must be determined early, based on the datasheet or interface specification. This facilitates layer allocation and track width definition, as each layer has unique resistance coefficients.
5. Decoupling Capacitors
Decoupling capacitors reduce noise in power/ground planes. High-frequency noise is best mitigated with decaps on the die, while adding 2–5 decaps per power supply in the package helps manage medium-range frequency noise. Decap values depend on factors such as data transfer rates, load capacitance, decap parasitics (Lc), and noise tolerance.
6. Track Shielding, Isolation, and Cross-Talk
Critical nets may require shielding to minimize cross-talk. These should be identified during substrate design. Analog signals should be isolated from digital signals or routed on separate layers, with shielding provided by a ground plane. Separate power and ground planes are recommended for analog and digital signals.
7. Electromigration Issues
Maximum current flow in any track depends on track width and material. Adequate track width is necessary to prevent high IR drops or electromigration issues. Via size must also be sufficient to avoid electromigration, even when track width is appropriate.
Mechanical Properties
The mechanical aspects of package design are crucial for estimating both the cost and the board's real estate. Package size and profile typically depend on die size, pin count, and other process parameters. Below are key factors to consider during the package development process:
1. Package Type (e.g., flip chip, wire bond)
The type of package is a foundational decision influenced by factors such as pin count, thermal conductance, reliability, cost, and yield. Flip chips generally support a higher pin count compared to wire bond packages and are commonly used for complex chips in flip chip BGA (Ball Grid Array) configurations. Emerging package types, such as Multi-Chip Modules (MCM), Package-on-Package (PoP), and System-in-Package (SiP), may also be considered based on specific requirements.
2. Package Size
Package size is primarily determined by die size and pin count. Each package has a die size limit, but in some cases, larger packages may be required to accommodate smaller dies with higher pin counts.
3. Die Orientation
For packaging houses processing whole wafers (whether bumped or not), die orientation is straightforward. However, when diced dies are sent for packaging, the company must be informed about die markings. Ideally, during layout, the die marking should consistently be placed at the same corner (e.g., top left). Pads are numbered starting from the top left corner and progress counterclockwise.
4. Package Thickness (Profile) Including Heat Spreader
Package thickness depends on die thickness, substrate thickness, and the number of layers in the package. High pin count packages or those with dedicated power/ground planes result in increased thickness. Integrated heat spreaders, when required, further contribute to overall package thickness.
5. Pin Count
Pin count is dictated by the number of I/O signals and power pins in the design, rather than the package itself. It is advisable to include spare pin capacity to accommodate future engineering change orders (ECOs) or additional power/ground pins. Modern FC-BGA packages can support over 2000 pins in a 23x23 mm package. Ball arrangement and the number of rows are typically defined by requirements. For example, a 25x25 ball package might feature a 6x6 center island, followed by a few empty rows and then populated rows.
6. Ball Pitch
Ball pitch refers to the distance between the centers of adjacent balls in BGA (Ball Grid Array) packages. Fine pitch packages provide smaller substrates, minimizing board real estate and reducing the risk of warpage during reflow. However, routing considerations on the board may dictate pitch size. Ball arrangements can be linear or staggered, with typical pitches in BGAs being 0.8 mm, 0.65 mm, and 0.5 mm.
7. Ball Size
Ball size represents the diameter of the external balls in BGA packages. For System-on-Chip (SoC) designs, typical ball sizes range from 0.3 mm to 0.65 mm.
8. Bond Fingers
Bond fingers are the contact points for bond wires on the substrate, connecting the I/O pads through the wires. These are generally arranged in a curved formation around the die. Their dimensions typically include:
Thermal Properties
Heat generated by the chip causes a temperature rise in the package. If the temperature of the chip (junction temperature) is beyond the design limitation, there could be some detrimental effects on the operation of the chip and the life of IC package. So it is necessary for a package to have sufficient heat dissipation capability. Now as the power density (power / chip area) increases, the thermal management is getting more critical. The most important factor in the thermal analysis is the power dissipation of the chip. It helps decide whether an integrated heat spreader is actually required in the package.
It is recommended to estimate the power consumption of the chip by adding the core power to the I/O power. The total power (Pic) is compared with the power that can be dissipated by the package in the form of heat. The following equation illustrates the power dissipation of the package:
PJA = (TJ - TA)/Theta JA
Where: PJA: Power dissipated (watt) TJ: Junction temperature, TA: Ambient temperature, Theta JA Package thermal resistance
If PJA is greater that PIC, it means the thermal performance of the package is adequate, and there won’t be a need to provide extra measures to dissipate more heat. In contrast, if PJA is less than PIC, further measures such as thermal vias, a fan or a heat sink must be considered. Also, contacting the back side of the die to the ground plane through a conductive epoxy could help reduce the temperature in the die.