think packaging when it comes to performance!
Consulting ServiceS for PKG development
IC Packaging
Overview:
Historically, silicon design and package design were treated as separate activities. Design teams often transferred a minimal subset of design data between platforms, a process that was manual, inefficient, and time-consuming. To minimize redesigns or iterations of the package substrate, package planning must begin early in the chip design phase, with active collaboration from package engineers. This includes estimating or defining factors such as die/package size, pin count, die thickness, I/O placement, power requirements, and signal integrity considerations.
Package specifications generally fall into three categories: mechanical, electrical, and thermal. These factors are interrelated and must be integrated into the design process rather than addressed in isolation. IC package development or substrate design process is outlined using a flowchart, which details the sequence of steps, along with the required input and output files at each stage. Typically, the package netlist includes a comprehensive list of bumps or bond pads with their x/y-coordinates, net names, balls, signals, impedance values, DC current requirements, and skew limits for balanced (matched) nets.
Electrical Properties
The electrical aspects of package design primarily address factors influencing chip performance and signal integrity. Below are key considerations in the package development process:
1. Package Type (e.g., QFN, flip chip BGA, wire bond)
2. Number of Layers
3. Number of Power/Ground Planes
4. Impedance Matching Per Layer
5. Decoupling Capacitors
6. Track Shielding, Isolation, and Cross-Talk
7. Electromigration Issues
8. Other factors
Mechanical Properties
The mechanical aspects of package design are crucial for estimating both the cost and the board's real estate. Package size and profile typically depend on die size, pin count, and other process parameters. Below are key factors to consider during the package development process:
1. Package Type (e.g., QFN, flip chip BGA, wire bond)
2. Package Size
3. Die Orientation
4. Package Thickness (Profile) Including Heat Spreader
5. Pin Count
6. Ball Pitch
7. Ball Size
8. Bond Fingers
Thermal Properties
Heat generated by the chip causes a temperature rise in the package. If the temperature of the chip (junction temperature) is beyond the design limitation, there could be some detrimental effects on the operation of the chip and the life of IC package. So it is necessary for a package to have sufficient heat dissipation capability. Now as the power density (power / chip area) increases, the thermal management is getting more critical. The most important factor in the thermal analysis is the power dissipation of the chip. It helps decide whether an integrated heat spreader is actually required in the package.
It is recommended to estimate the power consumption of the chip by adding the core power to the I/O power. The total power (Pic) is compared with the power that can be dissipated by the package in the form of heat. The following equation illustrates the power dissipation of the package:
PJA = (TJ - TA)/Theta JA
Where: PJA: Power dissipated (watt) TJ: Junction temperature, TA: Ambient temperature, Theta JA Package thermal resistance
If PJA is greater that PIC, it means the thermal performance of the package is adequate, and there won’t be a need to provide extra measures to dissipate more heat. In contrast, if PJA is less than PIC, further measures such as thermal vias, a fan or a heat sink must be considered. Also, contacting the back side of the die to the ground plane through a conductive epoxy could help reduce the temperature in the die.